1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to a method of making insulated-gate field-effect transistors and diffused resistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide the gate. Thereafter, the gate provides an implant mask during the implantation of source and drain regions, and the implanted dopants are driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to spacers adjacent to the gate. The spacers are typically oxides or nitrides. The purpose of the lighter dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The heavier dose forms a low resistivity heavily doped region of the drain. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. A known fabrication sequence includes forming lightly doped source/drain regions, forming the spacers, and then forming heavily doped source/drain regions. Another known fabrication sequence includes forming disposable spacers, forming heavily doped source/drain regions, removing the disposable spacers, and then forming lightly doped source/drain regions (between the heavily doped source/drain regions and the gate).
Disadvantages of LDDs include increased fabrication complexity and increased parasitic resistance due to their light doping levels. During operation, LDD parasitic resistance decreases drain current. Linear drain current (in the linear or triode region) is reduced by the parasitic resistance in both the source and drain. Saturation drain current (in the saturation region) is largely unaffected by the parasitic resistance of the drain but greatly reduced by the parasitic resistance of the source. Therefore, saturation drain current can be improved while reducing hot carrier effects by providing a lightly doped region only on the drain side. That is, the drain includes lightly and heavily doped regions, and the entire source is heavily doped.
Asymmetrical IGFETs (with asymmetrically doped sources and drains) are known in the art. For instance, U.S. Pat. No. 5,424,229 entitled "Method For Manufacturing MOSFET Having An LDD Structure" by Oyamatsu discloses providing a mask with an opening over a substrate, implanting a dopant through the opening at an angle to the substrate to form a lightly doped drain region on one side without a corresponding source region on the other side, forming a gate in the opening which overlaps the lightly doped drain region, removing the mask and implanting heavily doped source and drain regions using the gate as an implant mask. As another example, U.S. Pat. No. 5,286,664 entitled "Method For Fabricating The LDD-MOSFET" by Horiuchi discloses forming a gate, implanting lightly doped source and drain regions using the gate as an implant mask, forming a photoresist layer that covers the source side and exposes the drain side, depositing a single spacer on the drain side using liquid phase deposition (LPD) of silicon dioxide, stripping the photoresist, and implanting heavily doped source and drain regions using the gate and single spacer as an implant mask.
An important parameter in IGFETs is the threshold voltage (V.sub.T), which is the minimum gate voltage required to induce the channel. In general, the positive gate voltage of an N-channel device must be larger than some threshold voltage before a conducting channel is induced, and the negative gate voltage of a P-channel device must be more negative than some threshold voltage to induce the required positive charge (mobile holes) in the channel. There are, however, exceptions to this general rule. For example, depletion-mode devices already have a channel with zero gate voltage, and therefore are normally on. With N-channel depletion-mode devices a negative gate voltage is required to turn the devices off, and with P-channel depletion-mode devices a positive gate voltage is required to turn the devices off
If the source and body of an IGFET are tied to ground, the threshold voltage can be calculated as follows: EQU V.sub.T =.phi..sub.ms -2.phi..sub.f -Q.sub.tot /C.sub.ox -Q.sub.BO /C.sub.ox -.DELTA.V.sub.T (1)
where .phi..sub.ms the work-function difference between the gate material and the bulk silicon in the channel, .phi..sub.f is the equilibrium electrostatic potential in a semiconductor, Q.sub.tot is the total positive oxide charge per unit area at the interface between the oxide and the bulk silicon, C.sub.ox is the gate oxide capacitance per unit area, Q.sub.BO is the charge stored per unit area in the depletion region, and .DELTA.V.sub.T is a threshold lowering term associated with short-channel effects. Expressions have been established for these various quantities in terms of doping concentrations, physical constants, device structure dimensions, and temperature. For example, the work-function difference .phi..sub.ms varies as a function of the doping concentration in a polysilicon gate. Therefore, the threshold voltage depends on the doping concentration in the polysilicon gate.
Providing low resistance contacts for the gate, source and drain can be accomplished using refractory metal silicide. In one approach, a thin layer of refractory metal is deposited over the structure after forming the lightly doped source/drain regions and the spacers and the heavily doped source/drain regions, and heat is applied to form silicide contacts wherever the refractory metal is adjacent to silicon (including single crystal silicon and polysilicon). Thereafter, an etch is applied that removes unreacted refractory metal over the spacers to prevent bridging silicide contacts for the gate, source and drain. Various silicides, including PtSi, MoSi.sub.2, CoSi.sub.2 and TiSi.sub.2 have been used for this purpose. For instance, the sheet resistance of titanium silicide (TiSi.sub.2) is as low as 3 to 6 .OMEGA./sq, whereas heavily doped polysilicon exhibits a sheet resistance on the order of 15 to 30 .OMEGA./sq. Another advantage to this approach is that the silicide contacts for the gate, source and drain are formed simultaneously and are self-aligned by the spacers. This self-aligned silicide is sometimes referred to as "salicide."
After the silicide contacts are formed, typically an oxide layer is formed over the device, contact windows are etched in the oxide layer to expose the silicide contacts, one or more layers of metallization are deposited over the oxide layer and into the contact windows, the metallization above the oxide layer is removed to form metal plugs in the contact windows, and a metal-1 pattern is formed on the oxide layer that selectively interconnects the plugs. Additional interlevel dielectrics, metal plugs and overlying metal patterns (such as metal-2 through metal-5) can be formed in a similar manner.
Resistors can be classified as those fabricated in integrated circuits and as discrete components. Integrated resistors can be further classified as diffused resistors, thin-film resistors, epitaxial resistors, and pinch resistors. Diffused resistors are formed by doping or counterdoping a region of the semiconductor substrate, for instance by ion implantation or solid phase diffusion. Thin-film resistors are typically polysilicon, amorphous silicon, or metal alloys such as silicides. Epitaxial resistors are a region of an epitaxial surface layer of a substrate. Pinch resistors are a by-product of bipolar technology (or JFET technology) where the base-layer is pinched by the top emitter diffusion.
Diffused resistors in npn bipolar processes are formed by using the shallow diffusion for the transistor base and emitter regions, or by using doped epitaxial regions. In NMOS and PMOS processes, diffused resistors are formed using process steps that dope the source/drain regions. In complementary metal-oxide semiconductor (CMOS) processes, the N-well and P-well masks can be configured so that diffused resistors are formed by the well implants, punchthrough implants, and threshold adjust implants. The resistance of diffused resistors depends on the length, width, depth and sheet resistance of the diffusion, which are generally known with good accuracy. Design criteria for diffused resistors also include geometric factors, such as rounding comers subject to high current density.
A resistor-protect insulator is usually formed over a diffused resistor before depositing a refractory metal over the substrate. Otherwise, silicide would form on the entire the diffused resistor and render it useless. Typically, the resistor-protect insulator is formed after forming the source and drain by depositing an insulating layer over the substrate, forming a photoresist layer on the insulating layer, etching the insulating layer and removing the photoresist layer.
In semiconductor manufacturing, it is highly desirable to reduce the number of process steps. Accordingly, a need exists for an improved method of making an IGFET and a protected resistor with a reduced number of process steps, particularly where the method provides a lightly doped drain, silicide contacts for the gate, source and drain, selective doping for the gate in order to precisely control the threshold voltage, and the flexibility to form symmetrical or asymmetrical devices.